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Analog Verification >> Analog Functional Verification >> How to write script in VCS-MX?
https://designers-guide.org/forum/YaBB.pl?num=1452250895

Message started by Gp on Jan 8^th, 2016, 3:01am

Title: How to write script in VCS-MX?
Post by Gp on Jan 8^th, 2016, 3:01am

Hello,

I am working on AMS verification.I have a verilog/verilog-A file & spice file.verilog is top module & spice is middle.

here I attach a cadence AMS designer tool script.But I want to this script in synopsys VCS-MX.So,any have a idea?