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Design >> Analog Design >> Cascode current mirror load
https://designers-guide.org/forum/YaBB.pl?num=1455425049

Message started by robotist on Feb 13^th, 2016, 8:44pm

Title: Cascode current mirror load
Post by robotist on Feb 13^th, 2016, 8:44pm

Hi, my name is JH.
I am designing OTA. In order to high gain, I use cascode current
mirror load.
But when output common mode level is changed, rout also changes dramatically.
The attatched image is main problem of OTA.
How can I keep rout to be nealy constant with vout level changed?

Thanks for read.

Title: Re: Cascode current mirror load
Post by beetwee on Feb 14^th, 2016, 1:05am

What is the value of voltage VBias? I think the cascode transistor is in triode instead of saturation.

Title: Re: Cascode current mirror load
Post by robotist on Feb 14^th, 2016, 3:52am

Thanks for reply.
But I checked region of cascode device. Both transistors are in saturation region.

Title: Re: Cascode current mirror load
Post by ULPAnalog on Feb 14^th, 2016, 11:29am

Hello

Which process node is this? Perhaps the gds of the transistor is not nearly low enough around the operating point(?). How does Vdsat compare with Vds? I would try to bias it a bit deeper into saturation to make sure Vds does not affect operation significantly.

Thanks and regards

Title: Re: Cascode current mirror load
Post by raja.cedt on Feb 15^th, 2016, 7:46am

Hello-
You should have posted the operating point rather a std cascade stage in paint. You wrote impedance is changing with common mode, means devices are moving out of sat region. Best way is check your Vdsat and make sure your common mode I snot below 2*vdsat.
What is your ro at the point where you have biased? Multiply this with gm*ro of the cascade, should match reasonably close to your sim.