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Design >> Analog Design >> Process Variation Control for Subthreshold Devices
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Message started by ljp2706 on Feb 23^rd, 2016, 5:54pm

Title: Process Variation Control for Subthreshold Devices
Post by ljp2706 on Feb 23^rd, 2016, 5:54pm

I'm working on a circuit that has two subthreshold diode connected transistors. I believe these two devices have the most impact on the variation in the circuit (with a Monte Carlo Analysis). I think it would be due to the exponential dependence on threshold voltage in the subthreshold region. I've managed to reduce the effects of process variation everywhere else in the circuit, but I cannot think of a way to reduce the variation in the subthreshold portion of the circuit. Gate area is maximized in accordance to Pelgrom's Law, and I cannot use adaptive body biasing as this is a fully depleted SOI process.
This is my first time working with subthreshold devices as well as process/mismatch sensitive devices, any tips on design methodology would be greatly appreciated.

Title: Re: Process Variation Control for Subthreshold Devices
Post by RobG on Feb 27^th, 2016, 3:43pm

I don't know the details of your circuit, but about all you can do is making it bigger. If it is a mirror that means longer, if it is a diff pair it means wider. Doubling the current also allows you to double the size and keep all else equal.

Title: Re: Process Variation Control for Subthreshold Devices
Post by loose-electron on Feb 28^th, 2016, 1:48pm

give some more information about what you are trying to do and perhaps we can suggest alternative methods.

Title: Re: Process Variation Control for Subthreshold Devices
Post by vroy_92 on Jul 16^th, 2016, 10:39am

I have often used source degeneration for reducing Vth mismatch for subthreshold current mirrors in a DAC. Blows up area drastically but saves a lot on my DNL.