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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> Reading verilog a module's branch current https://designers-guide.org/forum/YaBB.pl?num=1459463210 Message started by AA on Mar 31st, 2016, 3:26pm |
Title: Reading verilog a module's branch current Post by AA on Mar 31st, 2016, 3:26pm I'm trying to probe the current flowing from output port "out" to output port "out1" in the following "cccs" module: module cccs(ctrl, in, in1, out, out1); input in, in1, ctrl; output out, out1; electrical in, in1, out, out1, ctrl; parameter real Ron = 1k; analog begin if (V(ctrl) == 0) V(out, out1) <+ 0; else I(out, out1) <+ I(in, in1)* I(in, in1) * Ron; end endmodule This module is instantiated as part of hspice netlist as follows: xI1 net5 n21 n31 0 net777 cccs I would like to examine the current of the current source between nodes 0 and net777. As an attempt to solve the problem myself, I added a probe statement to my hspice netlist as follows: .PROBE tran I5(xI1) However, hspice reports the following warning: **warning** only v and i function supported for va device: xi1 Is there another way around this please? Please note: this module is taken from this VA file http://nimo.asu.edu/memory/download/pcm/model.va and modified a little. |
Title: Re: Reading verilog a module's branch current Post by Geoffrey_Coram on Apr 4th, 2016, 8:35am try .PROBE tran i(xI1.out1) |
Title: Re: Reading verilog a module's branch current Post by Ken Kundert on Apr 4th, 2016, 3:23pm Code:
That is never a good idea. -Ken |
Title: Re: Reading verilog a module's branch current Post by AA on Apr 9th, 2016, 8:39pm Geoffrey_Coram wrote on Apr 4th, 2016, 8:35am:
Thanks Geoffrey_Coram! This seems to work. But another problem appears now: Note that the quantity I(xI1.out1)=I^2*R must always be positive (or always negative, depending on measurement direction). However, the quantity fluctuates between positive and negative values. Is this possible? Or am I doing something wrong? |
Title: Re: Reading verilog a module's branch current Post by AA on Apr 9th, 2016, 8:41pm Ken Kundert wrote on Apr 4th, 2016, 3:23pm:
Thank you for the comment Ken. I appreciate if you can explain why this is not a good idea. |
Title: Re: Reading verilog a module's branch current Post by Ken Kundert on Apr 11th, 2016, 12:43am It is almost never a good idea to do an equality test on real number. It is very unlikely to trigger. Worse, it it ever does trigger, the model switches its nature from being a current source to being a voltage source. I don't know what you are trying to model, but it is nothing that could exist in nature. Doing such things will just lead to simulation problems. Is there any reason why you have to output your computed quantity? You might be better served to simply save it in a local variable inside the module and then just plot that. -Ken |
Title: Re: Reading verilog a module's branch current Post by Geoffrey_Coram on Apr 11th, 2016, 9:27am AA wrote on Apr 9th, 2016, 8:39pm:
Is the value outside the tolerances? Eg, if abstol is the default 1pA, then any value less than 1pA is understood to be indistinguishable from zero. |
Title: Re: Reading verilog a module's branch current Post by AA on Apr 13th, 2016, 11:42am Ken Kundert wrote on Apr 11th, 2016, 12:43am:
Thanks, this is really very educating Ken. I did not write this module myself. This module is part of the phase change memory cell model by ASU (the verilog-a model is here: http://nimo.asu.edu/memory/download/pcm/model.va , the hspice testbench is here: http://nimo.asu.edu/memory/download/pcm/1t1r.sp , and the model manual is here: http://nimo.asu.edu/memory/download/pcm/manual.pdf ). The cccs module is meant for power consumption calculation. Ken Kundert wrote on Apr 11th, 2016, 12:43am:
The reason: I would like to measure the power consumption of the circuit during a period, and integrate that over time to calc the energy. Makes sense? I simply want to print (or probe) the verilog-a quantity I(out,out1) in hspice netlist. Both I(xI1.out) and I(xI1.out1) outputs something different. I know because I added a $display statement to output the verilog-a quantity I(out,out1), which is all positive as expected. Both I(xI1.out) and I(xI1.out1) are fluctuating between positive and negative. So, the question is: is there a way to ".print" I(out,out1) from within the hspice netlist? Ken Kundert wrote on Apr 11th, 2016, 12:43am:
Is there a way to do this from within the verilog-a module? By the way, I'm new to both hspice and verilog-a. |
Title: Re: Reading verilog a module's branch current Post by Ken Kundert on Apr 14th, 2016, 1:50pm You should be able to plot the value of your local variables, but unfortunately I have never used HSPICE, so I can give you no guidance as to how to do it. -Ken |
Title: Re: Reading verilog a module's branch current Post by Geoffrey_Coram on Apr 21st, 2016, 12:44pm For compact modeling, most of the local (internal) variables are not interesting, so we set up a special convention for declaring operating-point variables by using an attribute: (* desc="transconductance" *) real gm; Then "gm" should be available as op-pt info in the same way that you get op-pt info from a BSIM4 transistor. |
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