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Design >> Analog Design >> gm/id method
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Message started by JARVIS on Apr 9^th, 2016, 11:11am

Title: gm/id method
Post by JARVIS on Apr 9^th, 2016, 11:11am

Hi,
I'm using gm/id transistor sizing approach to design a low power opamp. I have a few questions regarding the same.
1) I biased the input transconductances in moderate inversion by choosing the gm/id of the differential transistors = 18, but while running dc simulation in cadence these transistors are shown to be biased in region 2 even though I get required gm. Is this correct? Will the transistors ever be in region 2 if they are in moderate inversion?

Title: Re: gm/id method
Post by ULPAnalog on Apr 9^th, 2016, 11:38am

Yes it is correct. It differentiates between strong inversion saturation and weak inversion saturation through region parameter being 2 and 3 respectively. For a gm/Id of 18 I would expect it to be on the verge of 2 and 3. You should see op region as 3 if you try to resize in such a way that gm/Id is around 22-25.

Title: Re: gm/id method
Post by JARVIS on Apr 9^th, 2016, 11:59am

okk thanks.
while sizing the transistors in the folded cascode, I used Vov = 2*id/gm and found the sizes from the gm/id lookup table. Since I used worst case condition currents, the dc simulation shows these transistors to be biased in region 2 but gm/id = 18 (since the current is less than worst case current) which implies that these transistors are close to subthreshold under normal bias conditions. Will this be a problem as these transistors should biased in strong inversion?

Title: Re: gm/id method
Post by ULPAnalog on Apr 9^th, 2016, 1:30pm

It depends on what your tolerances on specifications are. Or you could over design the transconductor stage so that it meets the specs even under worst case conditions.