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Simulators >> Circuit Simulators >> Fmax of MOS Transistor
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Message started by analog_design on Aug 11^th, 2016, 7:51am

Title: Fmax of MOS Transistor
Post by analog_design on Aug 11^th, 2016, 7:51am

Hello,

I'm trying to simulate Fmax of single MOS transistor in cadence. I am following guideline / test bench mentioned on cadence blog:

https://community.cadence.com/cadence_blogs_8/b/rf/archive/2010/12/07/measuring-transistor-fmax

But, when I plot Unilateral Power Gain from the device. It shows me weird behavior.
Can somebody please help me out ?

Thanks