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Design >> Analog Design >> Stacking of MOS to reduce random mismatch in a current mirror
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Message started by vroy_92 on Nov 7^th, 2016, 8:06pm

Title: Stacking of MOS to reduce random mismatch in a current mirror
Post by vroy_92 on Nov 7^th, 2016, 8:06pm

Why are identical MOSes used in a current mirror to reduce mismatch?
It is a common practice to stack devices to reduce random mismatch is a current mirror. The stacked devices behave like resistors, thus making the entire stacked structure behave like a source degenerated common source transistor. The effective gm reduces and thus current mismatch due to Vth mismatch comes down as well.
But it is not necessary to use the same width to get a MOS resistor which can effect source degeneration.