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https://designers-guide.org/forum/YaBB.pl Simulators >> Circuit Simulators >> How to enforce a syntax error when using an undeclared variable in HSPICE? https://designers-guide.org/forum/YaBB.pl?num=1479927062 Message started by AA on Nov 23rd, 2016, 10:51am |
Title: How to enforce a syntax error when using an undeclared variable in HSPICE? Post by AA on Nov 23rd, 2016, 10:51am When using a Verilog-A module in HSPICE, if you misspell a variable name, the module will compile and replace the misspelled variable with a 0. How can I make HSPICE throws an error and stop compilation when a misspelling of a variable name occurs (assuming the misspelled variable is not declared)? To reproduce the issue/point I'm talking about, here is an HSPICE netlist: Code:
And the "cut.va" resistor module: Code:
Note that HSPICE does not produce an error and just auto-declares a new variable with the same type initialized to 0: Code:
How to prevent the "auto-declare" functionality and mandate all variables to be explicitly declared? I hope there is an option for this. |
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