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https://designers-guide.org/forum/YaBB.pl Simulators >> RF Simulators >> Verilog-A hidden state in tran simulation and pss simulation https://designers-guide.org/forum/YaBB.pl?num=1479952162 Message started by ana2 on Nov 23rd, 2016, 5:49pm |
Title: Verilog-A hidden state in tran simulation and pss simulation Post by ana2 on Nov 23rd, 2016, 5:49pm Hi everyone I have some questions about Verilog-A hidden state. In usual transient simulation, Verilog-A hidden state is not a problem. But in PSS simulation, simulation fails if hidden state exist because of syntax check. Can anybody tell me why transient simulation is OK and PSS fails if hidden state exist? Maybe algorithm of transient simulation and PSS simulation is different. I will be appreciate if anybody can tell me some details. Best regards ana2 |
Title: Re: Verilog-A hidden state in tran simulation and pss simulation Post by Ken Kundert on Nov 23rd, 2016, 10:10pm Try reading http://www.designers-guide.org/Analysis/hidden-state.pdf and http://www.designers-guide.org/Forum/YaBB.pl?num=1471484004 -Ken |
Title: Re: Verilog-A hidden state in tran simulation and pss simulation Post by ana2 on Dec 5th, 2016, 7:47pm Hi ken Thanks for reply. I understand now SpectreRF can not handle [local state variables] with ordinary differential equations. Is that because Mathematical reasons or can be improved in future? best regards ana2 |
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