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Design >> Analog Design >> sub-threshold design of MOSFET for 45nm technology
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Message started by joy on Dec 17^th, 2016, 9:46pm

Title: sub-threshold design of MOSFET for 45nm technology
Post by joy on Dec 17^th, 2016, 9:46pm

Hi all,

I want to design a op-amp for 45nm technology which is operating in sub-threshold region
can any one give me the ID and gm equations which can be used for hand calculations in BSIM3 model, i am using a cadence virtuoso simulator .

Thank you

Title: Re: sub-threshold design of MOSFET for 45nm technology
Post by lpalocko on Jan 27^th, 2017, 3:56am

Hi,

why do you want to use exactly the BSIM3 model?

LP

Title: Re: sub-threshold design of MOSFET for 45nm technology
Post by Andrew Beckett on Jan 29^th, 2017, 1:01am

The model equations are documented in the MMSIM documentation - if you invoke <MMSIMinstDir>/bin/cdnshelp you'll find it under the "MMSIM" section in the documentation (I can't remember the manual name off the top of my head, but it's got something like Model Equation Reference in the title). There's a chapter on bsim3v3 and another on bsim4. Most likely any 45nm PDK (such as the Cadence Generic 45nm PDK, gpdk045) will use bsim4, not bsim3v3.

Regards,

Andrew