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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Loop filter Verilog AMS https://designers-guide.org/forum/YaBB.pl?num=1484928858 Message started by JeromeONeill on Jan 20th, 2017, 8:14am |
Title: Loop filter Verilog AMS Post by JeromeONeill on Jan 20th, 2017, 8:14am I'm new to Verilog AMS and I'm trying to write a simple script for a second order loop filter in Verilog AMS. Here is the code I have written so far, I am unsure how to join C2 to R1 in order to complete the filter. Thanks in advance //Verilog-AMS HDL for "PLLBehav", "Loop_filter" "verilogams" `include "constants.vams" `include "disciplines.vams" `include "Resistor.vams" `include "cap70pF.vams" `include "cap500fF.vams" module Loop_filter (p,n); ground gnd; inout p,n; electrical p,n,a; Resistor#(.r(5k))R1(p,a); cap70pF#(.c1(70p))C1(a,gnd); cap500fF#(.c2(500f))C2(n,gnd); endmodule |
Title: Re: Loop filter Verilog AMS Post by Ken Kundert on Jan 20th, 2017, 11:19am Add the following to create a 0V oltage source between p and n: Code:
I am surprised you have two different capacitor definitions. Aren't they the same? -Ken |
Title: Re: Loop filter Verilog AMS Post by JeromeONeill on Jan 21st, 2017, 9:57am Thank you for your help, I have two different capacitor values so I thought I needed two capacitor modules with the capacitance value for each capacitor declared within each capacitors module. Do I only need one module for a component even if I'm using more than one of them each having a different value? Thanks in advance -Jerome Ken Kundert wrote on Jan 20th, 2017, 11:19am:
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Title: Re: Loop filter Verilog AMS Post by JeromeONeill on Jan 21st, 2017, 10:00am Yes the definitions are the same, I see my mistake now thank you. - Jerome Ken Kundert wrote on Jan 20th, 2017, 11:19am:
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Title: Re: Loop filter Verilog AMS Post by Geoffrey_Coram on Jan 24th, 2017, 6:56am If you put V(p,n) <+ 0, doesn't that short out everything else in the module? |
Title: Re: Loop filter Verilog AMS Post by Geoffrey_Coram on Jan 24th, 2017, 7:00am According to Annex E (Spice Compatibility) of the Verilog-AMS LRM (version 2.4), you should be able to just instantiate Spice primitives like a resistor and a capacitor: Code:
There are also some voltage sources available: vexp, vpulse, vpwl, vsin (no vdc, but all of the sources have a dc parameter, so you just have to set the other parameters properly). |
Title: Re: Loop filter Verilog AMS Post by Peng_Li on Mar 23rd, 2017, 8:45pm Geoffrey_Coram wrote on Jan 24th, 2017, 7:00am:
Hi, Mr. Coram. It seems that the primitives Hspice supports doesn't include the voltage sources you just mentioned. The reason for this problem is likely to be the version of Verilog-AMS LRM. I am using Hspice-2009. It only supports, even Hspice-2014, Verilog-AMS LRM (version 2.2). Besides this feature, there are also other enhanced functions in later versions, which maybe useful for what I am doing. Could you give me some advice about which software supports the Verilog-AMS LRM of later version? (Those similar to Hspice would be easier for me to get started.) Thanks in advance. |
Title: Re: Loop filter Verilog AMS Post by JeromeONeill on Mar 24th, 2017, 7:40am Cadence Virtuoso supports Verilog A and Verilog AMS |
Title: Re: Loop filter Verilog AMS Post by Peng_Li on Mar 24th, 2017, 6:55pm JeromeONeill wrote on Mar 24th, 2017, 7:40am:
Sorry, I didn't make myself clear. I mean, the version of Verilog-AMS LRM that Hspice-2009 and Hspice-2014 support are version 2.2. The function of this version seems relatively limited. So I am looking for some software which support later version Verilog-A or Verilog-AMS. (Anyway, thanks for replying.) |
Title: Re: Loop filter Verilog AMS Post by Ken Kundert on Mar 24th, 2017, 11:59pm Quote:
No. It shorts nodes p and n, which essentially makes nodes p and n aliases of each other, but the capacitors and resistors are connecting from p/n to ground, those are not shorted. In general, I prefer not to use simulator primitives because they are very static. Specifically you cannot change their parameter values with time. I like the ability to do that. That may not be helpful in this situation, but it is really helpful in testbenches. -Ken |
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