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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> A simple question regarding some verilog code https://designers-guide.org/forum/YaBB.pl?num=1491359100 Message started by wandola on Apr 4th, 2017, 7:25pm |
Title: A simple question regarding some verilog code Post by wandola on Apr 4th, 2017, 7:25pm Hi all, I am wondering for the following code, at the rising edge of clk what is the output when A==0. thanks. :) //------------------ always @ (posedge clk or negedge rstn) begin if(rstn==0) out <= 0; else begin if (A==1) out<=IN1; else ; end End |
Title: Re: A simple question regarding some verilog code Post by Ken Kundert on Apr 4th, 2017, 11:57pm if rstn is 0 output is 0, otherwise it remains unchanged. -Ken |
Title: Re: A simple question regarding some verilog code Post by wandola on Apr 5th, 2017, 6:27pm got it. thanks Ken |
Title: Re: A simple question regarding some verilog code Post by skyer on Apr 21st, 2017, 12:06am I think it is unchanged. |
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