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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> Parsing of verilog-ams file produced warnings https://designers-guide.org/forum/YaBB.pl?num=1503032602 Message started by Lavanya on Aug 17th, 2017, 10:03pm |
Title: Parsing of verilog-ams file produced warnings Post by Lavanya on Aug 17th, 2017, 10:03pm I am new to verilog A coding and i got the following warning WDPS: Parsing of verilog-ams file produced warning but symbol has been created what would be the possibilities for such warnings.. Thank you |
Title: Re: Parsing of verilog-ams file produced warnings Post by Geoffrey_Coram on Aug 18th, 2017, 6:21am The simulator/compiler/parser is trying to help you out. It might be warning you of something that looks like a common mistake in your code, something that is not fully supported, something that will simulate poorly or inefficiently, etc. I would expect there to be more details of the warning in a log file, and we could help you more if you gave us those details. |
Title: Re: Parsing of verilog-ams file produced warnings Post by Lavanya on Aug 18th, 2017, 10:11pm Thank you for the reply sir.. This is the following log error for Parsing of verilog-ams file produced warnings. *W,SPDUSD (No source,0|0): Include directory /root/Desktop/MMM/ given but not used. ------ The command line specified an include directory to be look for tick-include files but is was never used. Please consider remove this directory from the command line for performance reason. |
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