The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> frequency divider with second order SDM has abs jitter of half vco https://designers-guide.org/forum/YaBB.pl?num=1503970844 Message started by cmosa on Aug 28th, 2017, 6:40pm |
Title: frequency divider with second order SDM has abs jitter of half vco Post by cmosa on Aug 28th, 2017, 6:40pm I have prepared a verilog a model for frequency divider with second order SDM. The divided frequency output has absolute jitter of half VCO cycle. I can not figure out why. Details of Model: 1. Started from integer frequency divider model from designer's guide. 2. modified it to accept N from a file 3. From my matlab code of SDM write N sequence to a file Simulation Setup: VCO clock (2.56GHz) fed to frequency_divider_sdm (fracN=0.5) Output: Output Frequency is correct 2.56G/98.5. However it has absolute jitter of half vco cycle. Please suggest me wherer I am going wrong |
Title: Re: frequency divider with second order SDM has abs jitter of half vco Post by cmosa on Aug 28th, 2017, 6:41pm Here is the code of frequency divider with sdm |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |