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https://designers-guide.org/forum/YaBB.pl Analog Verification >> Analog Functional Verification >> Assertions inside Connect Modules https://designers-guide.org/forum/YaBB.pl?num=1505747001 Message started by sgh2050 on Sep 18th, 2017, 8:03am |
Title: Assertions inside Connect Modules Post by sgh2050 on Sep 18th, 2017, 8:03am Hi All, I am new to AMS verification. I have following question. Please let me know if I can place assertions inside connect module for E2L. The purpose is to check that Signals coming from analog to digital are at 1.2 V level. This is to check that there are Level shifters in analog so that 3.3v is correctly converted to 1.2V before going to digital We use Cadence. How can i tell cadence irun to pick a a custom E2L connect module Best Regards |
Title: Re: Assertions inside Connect Modules Post by nischaybm on Nov 30th, 2017, 1:12am Hi sgh2050, I am not sure if you can add assertions, that may need you to have a clk signal. default connect module doesn't complain if the signal Voltage is higher than expected. you can right your own connect modules for this purpose, you can include them like them in ADE, ADE--> SETUP --> connect Rules Thanks, |
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