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https://designers-guide.org/forum/YaBB.pl Modeling >> Semiconductor Devices >> Transistor model with variable gate capacitance https://designers-guide.org/forum/YaBB.pl?num=1509272713 Message started by frasheed on Oct 29th, 2017, 3:25am |
Title: Transistor model with variable gate capacitance Post by frasheed on Oct 29th, 2017, 3:25am I am modeling a n-type transistor. I already have DC model in verilog-a format. This DC model doesn't have capacitance in it. I am extending it to add gate capacitance. In our process technology gate capacitance is variable (please see the attached image) and I have equation for gate capacitance. From figure, you can see that I have internal gate (ig) terminal which would be the final gate voltage for my transistor. I have a small problem, I only define current through resistor and capacitor using contributions equation: Code:
Now If I make an inverter logic using this extended model, if I increase the input voltage (from 0 to VDD) then Output first increase little bit over VDD and then decreases to low voltage (logic 0). I believe the output first increases because of CGD charging and when it is charge , the output gets decreased. Could anyone of you please tell me what is wrong with my modeling approach?.My gate capacitance realization is correct ? P.S: My capacitances values are in nF . Thanks |
Title: Re: Transistor model with variable gate capacitance Post by DanielLam on Oct 30th, 2017, 4:33pm If you're wondering about the overshoot, that is normal. There is also undershoot. You can see this by just trying out a normal inverter. Just have a sharp rise/fall time. |
Title: Re: Transistor model with variable gate capacitance Post by Geoffrey_Coram on Oct 31st, 2017, 10:28am frasheed wrote on Oct 29th, 2017, 3:25am:
You really should write your model in terms of gate charge. Current is dQ/dt, and for a linear capacitor, dQ/dt = C dV/dt, but for a nonlinear capacitor, this is no longer true. In particular, dC/dt is may be non-zero! |
Title: Re: Transistor model with variable gate capacitance Post by frasheed on Nov 2nd, 2017, 5:06am Hi Geoffrey_Coram, After changing it to gate charge, I am getting convergence error for inverter logic. Here is my complete code: Code:
Could you please review my code ?. The DC model is from anothe developer I just added capacitance block for transient simulation. |
Title: Re: Transistor model with variable gate capacitance Post by Geoffrey_Coram on Nov 2nd, 2017, 10:06am You have Code:
Cgs should be the partial derivative of Qs with respect to Vgs, but with what you have written, Code:
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Title: Re: Transistor model with variable gate capacitance Post by Geoffrey_Coram on Nov 2nd, 2017, 10:08am Code:
and what is 0.3e-9 ?? Regardless of the node voltages -- that is, even at zero bias -- you'll get 0.3nA of current. |
Title: Re: Transistor model with variable gate capacitance Post by frasheed on Nov 2nd, 2017, 10:18am Thank you for your reply. Geoffrey_Coram wrote on Nov 2nd, 2017, 10:06am:
Regarding your argument that Cgs should be partial derivative w.r.t Vgs. Could you please give me any hints or literature why it should be like this ?. I also found a mistake in my code, CS and CD are not equal, CS and CD values are calculated from different electrodes. This is what it look like now: Code:
Regarding 0.3e-9, The developer added it for testing purpose. We will remove it. |
Title: Re: Transistor model with variable gate capacitance Post by Geoffrey_Coram on Nov 3rd, 2017, 7:19am frasheed wrote on Nov 2nd, 2017, 10:18am:
M. A. Cirit, "The Meyer model revisited: Why is charge not conserved?", IEEE Trans. Comp.-Aided Des., vol. 8, pp. 1033-1037, Oct. 1989. P. Yang, B. D. Epler, P. K. Chatterjee, "An investigation of the charge conversation problem for MOSFET circuit simulation", IEEE Solid-State Circuits, vol. SC-18, pp. 128-138, 1983. D. E. Ward, R. W. Dutton, "A charge oriented model for MOS transistor capacitances", IEEE J. Solid-State Circuits, vol. SC-13, pp. 703-707, 1978. D. E. Ward, Charge-based modeling of capacitance in MOS transistors, 1981. |
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