The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Other CAD Tools >> Physical Verification, Extraction and Analysis >> Extract parameters for custom Verilog-A models https://designers-guide.org/forum/YaBB.pl?num=1509824847 Message started by georgtree on Nov 4th, 2017, 12:47pm |
Title: Extract parameters for custom Verilog-A models Post by georgtree on Nov 4th, 2017, 12:47pm Hello everyone! I faced with folowing problem: how can I extract parameters for my Verilog-A model ? All common models like BSIM, EKV, HiSIM and etc have default implementaions in programs like IC-CAP, MBP, UTMOS. But how can I use such tools for my handwritten models? Does anyone have such experience? Thank you for help! |
Title: Re: Extract parameters for custom Verilog-A models Post by georgtree on Dec 10th, 2017, 4:05am Does anybody know?( |
Title: Re: Extract parameters for custom Verilog-A models Post by Ziauddin on Jan 29th, 2019, 6:25pm You can put the verilog-A coded model into the defined directory of the ICCAP to read the verilog-A model. After that it just as before. For ICCAP the syntex in the circuit directory is: ahdl_include "/home/user/hpeesof/veriloga/models_name.va" Sorry, join the forum late. |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |