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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> simulating .va files in hspice https://designers-guide.org/forum/YaBB.pl?num=1552848227 Message started by masoumeh on Mar 17th, 2019, 11:43am |
Title: simulating .va files in hspice Post by masoumeh on Mar 17th, 2019, 11:43am Hi I'm working on simulating an ideal delta sigma modulator in hspice and I need to use ideal models for different parts of my circuit. for example I want to simulate the quantizer.va model in hspice for a 3rd level quantizer. I follow the manual for simulating this kind of models in hspice but unfortunately it is not working. I will appreciate if anyone can help me. the .va and .sp files are attached below and are written too. Also the problem is that when I simulate the test.sp in hspice nothing happen and the .lis file is empty and no error and other information is shown. . quantizer.va file: // N-level triggered quantizer (like an ADC followed by a DAC) // // Version 1b, 17 July 03 // // Ken Kundert // // Downloaded from The Designer's Guide (www.designers-guide.org). // Post any questions to www.designers-guide.org/Forum `include "disciplines.vams" module quantizer (out, in, clk); output out; voltage out;// output input in; voltage in; // input input clk; voltage clk; // clock input (edge triggered) parameter integer levels=2 from [2:inf);// number of quantization levels parameter real vh = +1; // voltage of highest level parameter real vl = -1 from (-inf:vh); // voltage of lowest level parameter real vth = (vh + vl)/2; // threshold voltage of clock parameter integer dir = +1 from [-1:+1] exclude 0; // if dir=+1, rising clock edge triggers // if dir=-1, falling clock edge triggers parameter real td = 0 from [0:inf); // output delay parameter real tt = 0 from [0:inf); // output transition time real quantized, delta; integer level; analog begin @(cross(V(clk) - vth, dir) or initial_step) begin delta = (vh-vl)/(levels-1); level = (V(in)-vl)/delta; if (level < 0) level = 0; else if (level >= levels) level = levels-1; quantized = level * delta + vl; end V(out) <+ transition( quantized, td, tt ); end endmodule test.sp file: Title: testing verilog-A .hdl quantizer.va .options post=1 VCLK clk 0 pulse 0 1 1f 1f 1f 0.390625u 0.78125u Vin in 0 SIN 0 1 2k Xquantizer1 out in clk quantizer levels=3 vh=1 vl=-1 vth =0 dir=1 td=0 tt=0 RL out 0 1meg .option method=gear post=1 .options delmax=10n .temp 25 .op .tran 10n 20m .end |
Title: Re: simulating .va files in hspice Post by Ken Kundert on Mar 17th, 2019, 3:12pm If you want help, it is probably best to simply show the .va and .sp files rather than force people to download and unpack them. Also, you should give the error message or at least describe what is going wrong. The way it currently stands, you are expecting people to do a bunch of work before they have any indication as to whether they can help you or not. |
Title: Re: simulating .va files in hspice Post by masoumeh on Mar 17th, 2019, 3:31pm Thank you for your comment, I edited the post. |
Title: Re: simulating .va files in hspice Post by Andrew Beckett on Mar 18th, 2019, 7:18am The main issue is that you have vth=0 on the instance line for the quantizer, and since the clock transitions between 0 and 1V, it never crosses the threshold. Set it to 0.5 instead. You also have your rise, fall and delay for the clock source set to the ridiculously short 1fs. That is going to make the simulator slower by trying to follow these unrealistically short transition times. Similarly you should set tt on the quantizer instance to be greater than 0. So I would suggest: Code:
I ran this in spectre (with the same netlist) and it then works fine. Even 100ps rise time/transition may be shorter than you really need if you've got a 1.28MHz clock. That said, for spectre it didn't affect the speed that much between 100p or 1n. Andrew. |
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