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Design Languages >> Verilog-AMS >> Timer statement inside a for loop
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Message started by knark on Mar 28^th, 2019, 2:09am

Title: Timer statement inside a for loop
Post by knark on Mar 28^th, 2019, 2:09am

Hello everyone,

I want to generate control signals that turn on a series of switches consecutively with a spacing of 1ps in between two consecutive signals going high.

My code :

`include "constants.vams"
`include "disciplines.vams"

module SourceResBank (p,n);

inout [1:2] p;
inout n;
electrical [1:2] p;
electrical n;

real expr [1:2];
genvar k;

analog begin

for (k=1 ; k<1+1 ; k=k+1)
begin

@(timer(0, 1))
expr[k] = 0;

@(timer(1p*k,1))
expr[k] = 1;

V(p[k]) <+ transition(expr[k]);
end

V(p[2]) <+ transition(expr[2]);
end

endmodule

The @timer statements inside the loop operate only once as the output p[1] gets a transition from low to high but the second (and third and so on) remain low.
However, if I write the @timer statements individually for all bits without the loop, that would work fine and all bits would transition from low to high.

Is there some restriction on timer statements in loops which only allows it to be operated only once ?

Title: Re: Timer statement inside a for loop
Post by knark on Mar 28^th, 2019, 2:41am

I found out I made a silly mistake in the code. There is no restriction on timer statements in a loop.