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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> [Solved] VerilogA - Branches and assignment https://designers-guide.org/forum/YaBB.pl?num=1571842725 Message started by saigoutham on Oct 23rd, 2019, 7:58am |
Title: [Solved] VerilogA - Branches and assignment Post by saigoutham on Oct 23rd, 2019, 7:58am Hi, I am new to Verilog-A and saw the following model for a Diode in Cadence's AMS reference manual. module diode (a, c) ; inout a, c ; electrical a, c ; parameter real rs=0, is=1e-14, tf=0, cjo=0, phi=0.7 ; parameter real kf=0, af=1, ef=1 ; analog begin I(a, c) <+ is*(limexp((V(a, c)-rs*I(a, a))/$vt) - 1); I(a, c) <+ white_noise(2* `P_Q * I(a, c)) ; I(a, c) <+ flicker_noise(kf*pow(abs(I(a, c)),af),ef); end endmodule How to read and understand this line? "I(a, c) <+ white_noise(2* `P_Q * I(a, c)) ;" I see I(a,c) is being used on both left and right side of the assignments. Thank you for the help. Regards, Sai. |
Title: Re: [Solved] VerilogA - Branches and assignment Post by saigoutham on Oct 23rd, 2019, 1:33pm I apologize for missing that these statements are evaluated "sequentially". I was thinking that these statements are part of a simultaneous equation |
Title: Re: [Solved] VerilogA - Branches and assignment Post by Geoffrey_Coram on Oct 24th, 2019, 6:11am To avoid the confusion you had initially, I would have written the module as id = is*(limexp((V(a, c)-rs*I(a, a))/$vt) - 1); I(a, c) <+ id; I(a, c) <+ white_noise(2* `P_Q * id) ; I(a, c) <+ flicker_noise(kf*pow(abs(id),af),ef); |
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