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Design >> Analog Design >> Split Array Capacitive DAC
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Message started by Bean Nakamura on Mar 16^th, 2020, 8:35am

Title: Split Array Capacitive DAC
Post by Bean Nakamura on Mar 16^th, 2020, 8:35am

Hello all,
Sorry if I sound dumb but I have a hard time convincing myself that the following capacitive circuits will work as a somewhat "capacitive divider".
I am well aware of the equation as per the texbooks and papers (for the left circuit) that the output voltage across C7 should be Vo = (C6/(C6+C7))*Vin.

Question:-
1) Shouldn't capacitors block DC values? If so wouldn't the value of Vin have no effect on value of Vout?

2)I'm trying to simulate a split array DAC capacitive (w/out the amp) as per the left figure. I've ran a quick DC analysis on Cadence but the as I suspected, the Vout across C5 isn't as what is expected from the textbook. In fact as per the figure, it's just zero volts. Am I missing something? Is there a setting somewhere to simulate these capacitive circuits that I might have left out (though to me it feels unlikely)?

Any suggestions are greatly appreciated. Thanks in advance!

Title: Re: Split Array Capacitive DAC
Post by mks on Mar 16^th, 2020, 9:50am

My understanding is when spice does DC analysis it opens Capacitors and shorts inductors. Also, remember there is gmin so the while calculating dc analysis the output node with the smaller impedance path to ground.

If you want to see the real transfer function I think ac analysis would be the right way. But remember it won't be accurate at lower frequencies because of gmin.

Regards

Title: Re: Split Array Capacitive DAC
Post by Bean Nakamura on Mar 16^th, 2020, 8:04pm

Hi mks,
Thanks for your reply. As per the books, it looks like they're annotating the DC output voltage instead of the gain, hence why I ran DC analysis. Anyway thanks for your insight!

Title: Re: Split Array Capacitive DAC
Post by Ken Kundert on Mar 17^th, 2020, 5:15pm

Capacitors do not pass DC signals, so you are not going to see anything using a DC analysis. Instead, you should run transient. Start with everything at zero and apply a step change in the input voltage.

In the real world the circuit will not be able to sustain the DC levels in the presence of leakage currents, so you can only count on the desired voltages to remain for a finite period of time.

A real version of this circuit would have switches across the capacitors to discharge them so they start in a known state.

-Ken

Title: Re: Split Array Capacitive DAC
Post by Bean Nakamura on Mar 17^th, 2020, 8:12pm

Hello Ken,
Thank you for your reply. Now that you've mentioned it, it does make a lot of sense. Will retry with the step response and simulate the transient. Thanks again!