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https://designers-guide.org/forum/YaBB.pl Modeling >> Behavioral Models >> Simple Inductor model in SystemVerilog using Cadence EEnet https://designers-guide.org/forum/YaBB.pl?num=1601665503 Message started by sanforyou on Oct 2nd, 2020, 12:05pm |
Title: Simple Inductor model in SystemVerilog using Cadence EEnet Post by sanforyou on Oct 2nd, 2020, 12:05pm I have a simple SV capacitor model using EEnet as shown below. This simulates with no issues when driven by 1V square wave as shown below: Code:
Output waveform is also attached for capacitor However I try to replicate inductor SV model using similar strategy as shown below: Code:
However, I see "Iout" and Vind both are zero all the time as shown in Inductor output waveforms. Can anyone explain why this model is not working? |
Title: Re: Simple Inductor model in SystemVerilog using Cadence EEnet Post by sanforyou on Oct 2nd, 2020, 12:06pm Also here are Inductor simulation waveforms |
Title: Re: Simple Inductor model in SystemVerilog using Cadence EEnet Post by Geoffrey_Coram on Oct 29th, 2020, 7:44am I have never used EEnet. Is it a Cadence-specific thing? I don't know what it means when you Code:
Have you tried putting in some print statements to debug? I assume Vind starts at 0, so that on the first step, dI = 0. How are you driving this model? Can you print P.V and verify that it is being driven? |
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