The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl Measurements >> Phase Noise and Jitter Measurements >> (Multi-modulus) divider phase noise simulation https://designers-guide.org/forum/YaBB.pl?num=1603971413 Message started by Nik21 on Oct 29th, 2020, 4:36am |
Title: (Multi-modulus) divider phase noise simulation Post by Nik21 on Oct 29th, 2020, 4:36am Hello everyone, Sorry if I missed the topic and the question is already answered. I want to simulate the phase noise contribution of an MMD used in a frequency synthesizer. For the purpose of simulation, the division is integer ( divide by N ). I use PSS and add Beat frequency to be Fvco/N ( where Fvco is the vco output frequency ). Also i add harmonics to be 5*N ( that would equal to 5 harmonics of Fvco). Then in Pnoise simulation , I use 10 maximum sidebands and add the voltage nodes I am interested in ( output nodes of MMD ). Im measuring relative harmonic 1 also. Is this the correct way to simulate a divider or am I missing something? Thank you in advance |
The Designer's Guide Community Forum » Powered by YaBB 2.2.2! YaBB © 2000-2008. All Rights Reserved. |