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Analog Verification >> Analog Functional Verification >> Query on a verilogA based pulse generation using a timer blocks.
https://designers-guide.org/forum/YaBB.pl?num=1623570657

Message started by subtr on Jun 13th, 2021, 12:50am

Title: Query on a verilogA based pulse generation using a timer blocks.
Post by subtr on Jun 13th, 2021, 12:50am

A simple periodic pulse generation :
1. Pulse repeats with period = clkPeriod.
2. A timer generated clkIn produces a clk whose rising edge is used to initiate the pulse, 'tLaunch' away from the clkIn edge.
3. Pulse is deasserted 'tRemove' away from the time of launch.
4. tLaunch + tRemove is ensured to be less than clkPeriod.


Code:
<verilogA>..
//Clock Generation
@(timer(nextEdge)) begin
clkIn = 1-clkIn;
nextEdge = nextEdge + 0.5*clkPeriod;
end

//Launch of pulse
@(timer(nextEdge+tLaunch)) begin
pulse = 1;
end
//Deassertion of pulse
@(timer(nextEdge+tLaunch+tRemove)) begin
pulse=0;
end


The above code doesn't produce the pulse. But there is a code change that can produce the pulse which I don't understand why.


Code:
//Clock Generation
@(timer(nextEdge+extraTime)) begin ... end


Could you please help in understanding what the issue is? This extraTime needs to be greater than the 'tLaunch' when I tried tweaking it.

Title: Re: Query on a verilogA based pulse generation using a timer blocks.
Post by Ken Kundert on Jun 13th, 2021, 9:49am

I wanted to help but I cannot understand your question.  Presumably what you are trying to accomplish is described at the top, but I cannot make any sense of it.  Also, the code is not complete, which makes things much harder.  I recommend that you come up with a complete example that is simple enough to be easily understood but also shows the problem, and then ask your question again, but this time be more careful about explaining what you want and what is going wrong.

-Ken

Title: Re: Query on a verilogA based pulse generation using a timer blocks.
Post by subtr on Jun 14th, 2021, 4:19am

Hi Ken,
Sorry for being vague. The thing is this is basically for generating a pulse with a periodic clock whose launch and deassertion can be varied. Now it's a constant, later planned to be used as a dynamic parameter. I have explained inline regarding the issue I'm facing. I do know to make it work. But I don't understand why it works or why the original code I wrote failed.

Code:
module myTimer(
output electrical pulse_out);
//variables
integer clk, pulse;
real period, nextEdge, tLaunch, tRemove;
analog begin

@(initial_step) begin
    clk = 1;
    pulse = 1;
    period = 10n;
    nextEdge = 10n;
    tLaunch = 3n;
    tRemove = 4n;
  end

//Clock Generation
@(timer(nextEdge)) begin //This argument seems to produce no pulse_out, while @(timer(nextEdge + period)) does. clk is generated in both cases
   clk = 1 - clk;
   nextEdge = nextEdge + period;
  end

//Pulse Generation
 @(timer(nextEdge + tLaunch)) begin
     pulse =1;
   end
 @(timer(nextEdge + tLaunch + tRemove)) begin
     pulse = 0;
   end

V(pulse_out) <+ transition(pulse,0,10p,10p);

end
endmodule

Title: Re: Query on a verilogA based pulse generation using a timer blocks.
Post by Ken Kundert on Jun 14th, 2021, 11:14pm

Still too vague.  Still don't know what you are expecting and what you are seeing.

For example, you can say: I am expecting the output to be a periodic clock with a period of 20ns that starts at 1 and where the first transition occurs at 13ns.

Something like that.

I did notice a few things.  First, you are computing clk but it is never used.  Second, you have a value called period, but the true period will be twice that value. Finally, it does not seem like pulse will ever change, because nextEdge updates to the future before it ever reaches nextEdge + tLaunch. It seems to me that the second two event statements will never trigger because the argument of their timer function is always in the future.

Maybe that is why changing the first event statement to nextEdge + period works.  It allows the second two event statements to trigger before the first pushes nextEdge into the future.

-Ken

Title: Re: Query on a verilogA based pulse generation using a timer blocks.
Post by subtr on Jun 14th, 2021, 11:32pm

Thank you Ken. I think I get the point you're raising. The triggering of the event is never occuring as the next edge gets updated to future before the second set of events could trigger.
I think the takeaway for me is that updation of nextEdge should always be the last thing in the chain of events so that we allow the events to trigger followed by the nextEdge definition. This is only a block to start with for me. That clock is also going to be one of the outputs in future. I wrongly thought that the event doesn't take the new value till it gets fired with the first value. delaying it by one period, allowed the other events to execute only after which the nextEdge got updated.

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