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https://designers-guide.org/forum/YaBB.pl Design >> Mixed-Signal Design >> Loop filter For PLL https://designers-guide.org/forum/YaBB.pl?num=1632321294 Message started by Vikrant on Sep 22nd, 2021, 7:34am |
Title: Loop filter For PLL Post by Vikrant on Sep 22nd, 2021, 7:34am Hello, I am doing Behavioral Modelling of PLL using Verilog-ams. I have use Laplace function for loop filter. My error signal (output of the filter) which is the input of VCO is going beyond VDD. How can I keep it below or equal to VDD. Below is the code //"verilogams" `include "constants.vams" `include "disciplines.vams" module analog_lapalce_filter (in,out); parameter real R=1K; parameter real C1=1p; parameter real C2=1p; input in; output out; electrical in,out; analog begin V(out)<+ laplace_nd( V(in), { R*C1,0},{R*C1*C2,C1+C2,0} ); end endmodule I have also attached the loop_filter which I am using. Thank you for your help in advance! |
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