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https://designers-guide.org/forum/YaBB.pl Simulators >> AMS Simulators >> how to set initial state of digital circuit in AMS simulation? https://designers-guide.org/forum/YaBB.pl?num=1637310434 Message started by unaffected on Nov 19th, 2021, 12:27am |
Title: how to set initial state of digital circuit in AMS simulation? Post by unaffected on Nov 19th, 2021, 12:27am I am using cadence AMS to do mixed signal simulation(analog circuit + digital circuit(verilog.v)), in digital cicuit, some DFFs used in frequency divider do not have initial reg value, the reg initial value should be set to avoid X state. Would someone teach me how to set all regs' initial value to 0 or 1? Many thanks. |
Title: Re: how to set initial state of digital circuit in AMS simulation? Post by Geoffrey_Coram on Feb 10th, 2022, 1:46pm Do you have the DFF model, can you edit it to allow specification of an initial reg value? |
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