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https://designers-guide.org/forum/YaBB.pl Design Languages >> Verilog-AMS >> genvar for loop instantiation https://designers-guide.org/forum/YaBB.pl?num=1671422497 Message started by Shubham_Kumar on Dec 18th, 2022, 8:01pm |
Title: genvar for loop instantiation Post by Shubham_Kumar on Dec 18th, 2022, 8:01pm While modelling a VCDL need to instantiate 40 delay cells. Following code gives error during compilation // VerilogA for DLL_behavioural_vams, vcdl, veriloga `include "constants.vams" `include "disciplines.vams" module vcdl(Phi, CK_in, Vctrl); input Vctrl, CK_in; electrical Vctrl, CK_in; output [39:0] Phi; electrical [39:0] Phi; delay_cell dcell0(Phi[0], CK_in, Vctrl); for(genvar i=1; i<40; i = i+1) begin delay_cell dcell(Phi[i], Phi[i-1], Vctrl); end endmodule Log file contents : Reading file: /user_data1/mtech/18IE34001/work_umc_180/DLL_behavioural_vams/vcdl/veriloga/veriloga.va Reading file: /software/eda/cadence/installed_bds/SPECTRE171/tools.lnx86/spectre/etc/ahdl/constants.vams Reading file: /software/eda/cadence/installed_bds/SPECTRE171/tools.lnx86/spectre/etc/ahdl/disciplines.vams Error found by spectre during AHDL compile. ERROR (VACOMP-2259): "for<<--? (genvar i=1; i<40; i = i+1) begin" "/user_data1/mtech/18IE34001/work_umc_180/DLL_behavioural_vams/vcdl/veriloga/veriloga.va", line 15: syntax error. ERROR (VACOMP-1814): Maximum allowable errors exceeded. Exiting AHDL compilation.... What is possibly going wrong :-/? getVersion() "@(#)$CDS: virtuoso version 6.1.7-64b 12/16/2018 07:36 (sjfhw317) $" getVersion("virtuoso") "sub-version IC6.1.7-64b.500.23 " |
Title: Re: genvar for loop instantiation Post by jbdavid on Dec 18th, 2022, 10:24pm The error message is flagging "for" which I think needs to be included inside some form of block, maybe a generate block? Good luck |
Title: Re: genvar for loop instantiation Post by Shubham_Kumar on Dec 18th, 2022, 11:06pm I added the for in generate ... endgenerate block. Still getting the same error ! Not sure what exactly is the problem... // VerilogA for DLL_behavioural_vams, vcdl, veriloga `include "constants.vams" `include "disciplines.vams" module vcdl(Phi, CK_in, Vctrl); input Vctrl, CK_in; electrical Vctrl, CK_in; output [39:0] Phi; electrical [39:0] Phi; delay_cell dcell0(Phi[0], CK_in, Vctrl); generate for(genvar i=1; i<40; i = i+1) begin delay_cell dcell(Phi[i], Phi[i-1], Vctrl); end endgenerate endmodule |
Title: Re: genvar for loop instantiation Post by Geoffrey_Coram on Mar 6th, 2023, 7:53am I don't think Verilog-AMS allows variable declarations inside the for-loop: you need to declare genvar i; beforehand. genvar i; for(i=1; i<40; i = i+1) begin |
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