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Design Languages >> Verilog-AMS >> [Need help] Concatenate integer arrays
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Message started by Shahriar on Jul 18^th, 2023, 8:02pm

Title: [Need help] Concatenate integer arrays
Post by Shahriar on Jul 18^th, 2023, 8:02pm

Hi,

I'm trying to concatenate two integer arrays in a verilog-A code. My code is as follows:

`include "constants.vams"
`include "disciplines.vams"

module scratch (out);

output out;
electrical out;

integer a[2:0] = {1,2,3}, b[3:0] = {1,2,3,4};
integer c[7:0], k;

analog begin

c = {a,b};

for (k=0; k<3; k=k+1) begin
$strobe("a[%d] = %d", k, a[k]);
$strobe("b[%d] = %d", k, b[k]);
$strobe("c[%d] = %d", k, c[k]);
end

V(out) <+ 0;

end

endmodule

But I get the following error - " The target of the assignment is a vector. Specify a scalar as the target of the assignment."

Could anyone please help me understand this or show me how to fix it?

Thanks.

Title: Re: [Need help] Concatenate integer arrays
Post by Geoffrey_Coram on Aug 30^th, 2023, 5:57pm

I think this may not be supported by the language. In the VAMS LRM, section 5.7, it says,
— Concatenation expressions cannot be used as part of the analog_expression (assigning to list of values in the analog context is not allowed).