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Analog Verification >> Analog Functional Verification >> How to parametrize input bits of a DAC in Verilog A code
https://designers-guide.org/forum/YaBB.pl?num=1696579849

Message started by Andrea8888 on Oct 6^th, 2023, 1:10am

Title: How to parametrize input bits of a DAC in Verilog A code
Post by Andrea8888 on Oct 6^th, 2023, 1:10am

Hi All,

as written in the subject, in case i want to leave the number of bits as parameter that user can choose in every run without changing the code ..: how to do it?
Which is the syntax to leave inputs / outputs of an istance as parameter?

Thanks in advance for the help

Title: Re: How to parametrize input bits of a DAC in Verilog A code
Post by Ken Kundert on Oct 6^th, 2023, 10:22am

Take a look at https://designers-guide.org/verilog-ams/functional-blocks/data-converter/converter-lrm.vams

However, be aware that you cannot use such a model in a Cadence schematic. Schematics do not allow the number of lines in a wire to be variable.