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Design >> Mixed-Signal Design >> System verilog modeling and simulation in cadence
https://designers-guide.org/forum/YaBB.pl?num=1738884744

Message started by Yashas on Feb 6^th, 2025, 3:32pm

Title: System verilog modeling and simulation in cadence
Post by Yashas on Feb 6^th, 2025, 3:32pm

Hi everyone,
I am new to system verilog modeling and my task is to model the 741 opamp using system verilog in as much detail as possible.

I was able to create a simple verilog description code, but the ADE simulator does not support simulating system verilog, a "corrupt netlist" notification pops up and after going through a couple of online material apparently spectre does not simulate system verilog.

Could some one recommend the appropriate steps to simulate the same on ADE or if there is an alternate tool that can be used?

FYI. I am limited to the DFII framework on cadence through the license my university uses. Other AMS tools are unavailable to me.

Thank You.