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General >> Tech Talk >> Help with 3 Key Questions on Analog Circuit Design & Verification
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Message started by Vodka_JON7 on Oct 14^th, 2025, 1:01am

Title: Help with 3 Key Questions on Analog Circuit Design & Verification
Post by Vodka_JON7 on Oct 14^th, 2025, 1:01am

Hi everyone,

I’m currently working on analog circuit design and verification and have run into a few confusing points. I’d really appreciate it if anyone with experience could share their insights! Here are my questions:

1. Most specs for analog circuits focus on performance. When we design circuits like LDOs, opamps, or PLLs, our core goal is essentially to create circuits with sufficient performance. If a circuit fails to meet the predefined performance metrics, it’s considered unqualified in the system. Conversely, a circuit that meets performance requirements will also fulfill its intended system functions. This makes me wonder: How do we distinguish between "performance" and "function" for analog circuits?

2. Is UVM-MS the ultimate solution for analog and mixed-signal verification? In a way, simulations like AC, DC, stb, and noise analysis all represent different perspectives on transient simulations. However, UVM-MS focuses more heavily on tran simulations. This leads me to ask: Can the UVM-MS framework replace traditional analyses like AC, STB, or PSS simulations? When I use UVM-MS, I keep questioning whether it covers everything needed. I also want to understand: What’s the fundamental difference between relying on UVM-MS versus using AC/PSS/STB simulations?

3. For analog circuits in general, how do we build a complete verification flow? And more practically, how can we prove that a designed analog circuit is truly qualified? This is another key confusion I haven’t been able to resolve.

Thanks in advance for any advice or discussions—your input would be a huge help!

Best Regards
Lewis