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Measurements >> Phase Noise and Jitter Measurements >> Question on Jitter Prediction Methodology
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Message started by Lieutenant Columbo on Sep 21^st, 2002, 10:22pm

Title: Question on Jitter Prediction Methodology
Post by Lieutenant Columbo on Sep 21^st, 2002, 10:22pm

Thanks a lot for the chance to ask you questions. I have read your series of papers on modeling and predication of phase noise and jitter on PLL-based frequency synthesizers. Here is my question:

Once one extracts the parameters of each of the blocks that constitute a PLL frequency synthesizer (n, fc, etc) the same parameters are fed to a Verilog-A module of each block and then the whole synthesizer is simulated. If I understood correctly, the methodology extracts the parameters in open-loop mode and then simulates the synthesizer in closed-loop. How am I sure that the dynamics of the closed-loop simulation is simulated correctly from open-loop extractions/simulations? In other words, what is the error margin of the simulations of the whole system knowing that the parameters were extracted from isolated modules?

I hope I am clear enough and sorry if the question is too obvious.
Best regards

Title: Re: Question on Jitter Prediction Methodology
Post by Ken Kundert on Sep 22^nd, 2002, 10:45pm

Actually, the question you ask is a very fundamental one, one that is at the heart of all modeling and simulation efforts.

With a simulation one takes a collection of models (a collection of equations that describe the components) and assembles them into a system (a large system of equations) and solves them. The way I see it, there are only two things that can go wrong and result in you getting the wrong answer. Either one or more of the component models is wrong, or the way that you combined the model equations into a larger system and solved them is wrong. The act of assembling and solving the system of equations is the core of what simulators do, and they have been doing it in the same basic way for a long time. They may break down, but that only happens if you excite a bug or present the simulator with a pathological case. They are approximate, and in some cases their accuracy is not sufficient. However, in general they have proven themselves to be quite robust.

So I believe the question that you are really asking is how do you know that your model is correct. Except for trivial models, one usually never knows for sure whether their model is correct. The risk of error is reduced by careful model development and validation.

Even with this, there is still a good chance the simulations of the overall system are wrong. If the system puts the models into a region that the original model developer did not anticipate and is not adequately modeled, then the overall results will be erroneous. So it is important that the model developer understand the end application for the model, and that the models be validated at least in systems similar to one being simulated.

With the PLL jitter models we have several things going for us.

The application area (PLL synthesizers) is fairly well understood.
The models were designed with the end application in mind.
The models were assembled into at least one frequency synthesizer and gave results that match, at least conceptually, what one would expect.

However, you should be aware that I have never validated the models against silicon, so there is still a good chance the models are flawed in some way.

Sorry, I got rather long winded. Hope I answered your question.

-Ken