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Simulators >> RF Simulators >> Hidden state in SpectreRF
https://designers-guide.org/forum/YaBB.pl?num=1033111507

Message started by Ken Kundert on Sep 27^th, 2002, 12:25am

Title: Hidden state in SpectreRF
Post by Ken Kundert on Sep 27^th, 2002, 12:25am

This is just to let everyone know that I have added a short paper to www.designers-guide.com/Analyses that discusses the hidden-state limitation for Verilog-A when running with SpectreRF. The paper describes the extent and reason for the limitation, presents a general approach to avoiding the problem, and gives two models, a track and hold, and a divider, that do not have hidden-state and so work with SpectreRF.

Enjoy,
-Ken

Title: Re: Hidden state in SpectreRF
Post by gashish on Feb 14^th, 2003, 12:03pm

Hi All,

I have written a model for 8-psk modulator in verilog-A(Eventually,developed it into a EDGE source).

The problem is that the model has a hidden state and hence cannot be used for envelope following analysis in spectreRF.It basically generates a symbol randomly at every specified interval.This symbol needs to be "remembered".
The part of the code looks something like this:
*********************************************************
module psk8(viout,vqout)
.
.
//random symbol generation
@(timer(start_bit_time,symbol_period)) begin
symbol_data=abs($random % 8);
end
.
.
V(viout) <+ cos((2*symbol_data)*`PI/8);
V(vqout) <+-sin((2*symbol_data)*`PI/8);
**********************************************************

I have tried the approaches mentioned in Ken's above document.But they dont seem to be helpful when the "hidden state" takes random values at specified intervals.

I would appreciate any tips/help in this regard.
Has anybody tried writing baseband source generators in verilog-A and then used them in envelope following analysis of spectreRF?

Thanks,
Ashish

Title: Re: Hidden state in SpectreRF
Post by gashish on Feb 14^th, 2003, 12:14pm

I guess i didnt disable smileys while posting the above post.

Anyways, they are basically the number EIGHT.
smileys=EIGHT

Thanks
Ashish

Title: Re: Hidden state in SpectreRF
Post by Eugene on Feb 14^th, 2003, 8:10pm

You could try a two step approach that is especially useful if you are not changing the baseband modulator very often. You could store the 8-psk baseband waveforms in two files, then replace the 8-psk model in your envelope analysis with a couple of Spectre primitive sources that read the files you just created. This is an especially cool approach if your baseband data is generated by another group and with another tool. You need only make sure the recorded data is in the proper format. If you still want to use your 8-psk generator, you can include write statements in your veriloga module to record the data.

P.S. It is a little known fact that the Spectre primitive sources also recognize SPW format. If you are using SPW for your baseband work, you can simply point the Spectre source to the ascii file created by an SPW signal sink without worrying about incompatible formats. That does not mean you have to record your data in SPW format. The sources understand both a simple two column format and the SPW format.

Title: Re: Hidden state in SpectreRF
Post by Frank Wiedmann on Feb 17^th, 2003, 12:20am

Normally, you can store a value as an internal capacitor voltage. See the posting of ronv at http://www.designers-guide.com/Forum/?board=rfsim;action=display;num=1033687038.

However, in your case this is probably not possible because the sampling operation requires some finite time, but the $random function generates a new value at each timestep.

Title: Re: Hidden state in SpectreRF
Post by Eugene on Feb 17^th, 2003, 11:32am

If you really want to use the baseband hidden state modulator in an envelope analysis, you could also try a resettable integrator. I've skirted the hidden state issue before with a resettable integrator (idt) statement. Integrate zero, set the initial condition to the desired state value, then assert the reset control during an aperture time. This is very similar to the capacitor idea but you don't have to play with capacitor values. The resettable integrator is a track and hold device. It tracks the initial condition as long as the assert command is high. If I recall, the trick is to make sure the assert command is not itself a state variable. i.e. you must ensure that it does not retain its value from one time point to the next.

I still favor the two-step approach using Spectre primitive sources. The only thing to watch out for is the spectrum about the harmonics of the sampling period. Spectre will linearly interpolate between sampling points and that introduces a first order hold operation that is probably not there physically. If you are interested in whether your analog filters properly suppress the images about the baseband sampling frequency, you will want to pay close attention to how the DAC really works. You can sample and hold the data but that again involves hidden state. The alternative I've used before is to use a sample rate that is 10 times the baseband sample rate to generate the baseband data that will be read in by the Spectre sources. The oversampling trick ensures that the waveform represents a real DAC output in that it has a staircase nature to it.

Another to be aware of if you are indeed looking at spectral mask or acpr, is to strobe the data and use the correct PSDbb parameters. The Cadence SpectreRF user's guide discusses these issues. Look under transmitter acpr. If you are not careful in how you postprocess the data, you will not see the right noise floor.