The Designer's Guide Community Forum

The Designer's Guide Community Forum
https://designers-guide.org/forum/YaBB.pl
Design >> Mixed-Signal Design >> gm-C tuning PLL design spec.
https://designers-guide.org/forum/YaBB.pl?num=1036155332

Message started by RC on Nov 1^st, 2002, 4:55am

Title: gm-C tuning PLL design spec.
Post by RC on Nov 1^st, 2002, 4:55am

i am designing a PLL circuit for the tuning circuit for a gm-C filter.
i design a third order PLL, where the second order loop filter is used.
i have searched through the literature, there are a lot of PLL theory, design etc. However, none about the design specification about the tuning circuit with PLL.
I have a few problem,
1.) how to estimate the settling time of the PLL? i simulate the PLL with transient simulation, and check the loop filter output, it gives me the settling time. But, what parameters in the derivation of the transfer function of the PLL determine the settling time in third order, or forth order, and even the second order?
2.) i estimate the tuning range of the filter from the VCO sensitivity, may i do in this manner?
3.) i use the control signal of the VCO to control the filter, than how to determine the noise inject into the filter? many PLL literature discuesses the noise after the VCO, for synthesiser. How's the effect of the phase noise? jitter etc. is it phase noise and jitter are the same?
4.) how large the lock/capture range required? how to estimate the lock/capture range? if can't be manual estimate, how to simulate this condition? i try to change the reference frequency and than check whether it will be locked, but not yet got any conclusion?
5.) is that the reference frequency suppression using forth order loop filter is required here. i guess no, but is it truth?

Thanks.

Title: Re: gm-C tuning PLL design spec.
Post by Eugene on Nov 2^nd, 2002, 4:09pm

Have you looked at W. Egan's book? It has some material on estimating transients and lock ranges.
"Phase-Lock Basics" by William F. Egan. ISBN0-471-24261-6.

If you are using Cadence tools, Cadence has some PLL models capable of quickly simulating transients and lock ranges. They are located in dfII/samples/artist/pllLib and documented near the end of the SpectreRF user's guide.

There's also a book with a chapter on a phase domain model of a PFD that might help. The book is
"Analog and Mixed-Signal Hardware Description Languages", edited by Alain Vachoux, Jean-Michel Berge, Oz Levia, and Jacques Rouillard. Check out chapter 5. ISBN # 0-7923-9875-0.