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Modeling >> Semiconductor Devices >> Hspice conversion
https://designers-guide.org/forum/YaBB.pl?num=1049951926

Message started by kimsm on Apr 9^th, 2003, 10:18pm

Title: Hspice conversion
Post by kimsm on Apr 9^th, 2003, 10:18pm

Hi, Ken

I have some question about spectre format.

I want conversion of hspice format sub-circuit into spectre format sub-circuit.
As I know spectre is not support V(n1,n2) (voltage-drop of n1-node and n2-node).

Below equation is hspice format circuit :

>> .subckt nmos_rf nd ng ns nb lr=length wr=width nr=finger
>> m0 nd ngi ns nbi nch w="wr*nr" l=lr ad=0 as=0 pd=0 ps=0
>> rgx ng ngi "(127.02+(86.55*lr*1e6))/(nr+1.9) + (-0.22+2.5*lr*1e6)"
>> cgd ngi nd "((0.45+1.5*lr*1e6) + ((1.06+0.89*lr* 1e6)*nr))*1e-15"
>> cgs ngi ns "((-9.74+73.05*lr*1e6) + (0.97+1.57*lr* 1e6)* nr)*1e-15"
>> cjd nd nbi "(((7.81-16.2*lr*1e6) + ((0.29+4.78*lr *1e6)*nr))*1e-15)/pwr((1+(v(nd,ns)/0.6791)),0.3529)"
>> cjs ns nbi "((-7.46+3.34*nr)*1e-15)"
>> rsubx nbi nb "(12.67*nr+1954.1)/(nr+8.26)"

>> .ends lvn

I want to conversion functions above, is possible?

send your opinion, please... i'll wait. good bye

Best Regards

;D

Title: Re: Hspice conversion
Post by Ken Kundert on Apr 9^th, 2003, 11:18pm

First, create a file for the subckt. I called it lvn.m. You can call it whatever you like.

Code:

// Model file for LVN
simulator lang=spectre
ahdl_include "nonlincap.va"
parameters length=?? width=?? finger=??

subckt lvn (nd ng ns nb)
parameters lr=length wr=width nr=finger
Mcore (nd ngi ns nbi) nch w=wr*nr l=lr ad=0 as=0 pd=0 ps=0
Rgx (ng ngi) resistor r=(127.02+(86.55*lr*1e6))/(nr+1.9)+(-0.22+2.5*lr*1e6)
Cgdx (ngi nd) capacitor c=((0.45+1.5*lr*1e6)+((1.06+0.89*lr*1e6)*nr))*1e-15
Cgsx (ngi ns) capacitor c=((-9.74+73.05*lr*1e6)+(0.97+1.57*lr*1e6)* nr)*1e-15
Cjdx (nd nbi nd ns) nonlincap c0=(((7.81-16.2*lr*1e6)+((0.29+4.78*lr*1e6)*nr))*1e-15)
Cjsx (ns nbi) capacitor c=((-7.46+3.34*nr)*1e-15)
Rsubx (nbi nb) resistor r=(12.67*nr+1954.1)/(nr+8.26)
ends lvn

Next, create a Verilog-A file for the nonlinear capacitor. I called it nonlincap.va.

Code:

module nonlincap (p, n, ps, ns);
electrical p, n;
parameter real c0 = 1e-15;
parameter real alpha=0.6791;
parameter real beta=0.3529;
real c;

analog begin
c = c0/pow(1+V(ps,ns)/alpha, beta);
I(p,n) <+ ddt(c*V(p,n));
end
endmodule

There are two issues that you need to be aware of with this model. First, Cjsx will be negative if nr < 2. That would be bad. It would generally result in making the circuit unstable, which would cause the simulator to fail. Second, in the nonlinear capacitor, the capacitance becomes negative when V(ps,ns)<-alpha. Again, that is bad.

-Ken