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Simulators >> Circuit Simulators >> Device noise simulation of Sigma Delta modulator
https://designers-guide.org/forum/YaBB.pl?num=1053631909

Message started by jwang on May 22^nd, 2003, 12:31pm

Title: Device noise simulation of Sigma Delta modulator
Post by jwang on May 22^nd, 2003, 12:31pm

Hi, Ken,
This is a great paper to help jump start the modeling of sigma delta modulator. However, unlike other of your papers, it left out the veriloga code and matlab scripts that can be very helpful to the interested reader to run simulations.
Your papers stand out of the rest of great publications in such a way that they not only help the reader understand the topic but also help the reader actually do it, smell it and taste it.
I wonder if you would post the veriloga code, matlab scripts, and spectre netlist needed to reproduce the results covered in this paper.
Best regards.

Jeff

Title: Re: Device noise simulation of Sigma Delta modulat
Post by Ken Kundert on Jun 2^nd, 2003, 9:38pm

I have uploaded the matlab scripts and verilog-a files for this paper. You can find them in http://www.designers-guide.com/Analysis/index.html.

There is not a lot of documentation on the scripts. They are offered 'as is'. It would be great is someone would like to improve them by creating documentation. If you do so, please send it to me and I will add it to the site.

-Ken

Title: Verilog-A model for ideal sample-and-hold
Post by Frank Wiedmann on Jun 3^rd, 2003, 4:21am

Hi Ken,

Would you mind publishing the Verilog-A code for the ideal sample-and-hold from your other recent paper "Simulating Switched-Capacitor Filters with SpectreRF" (http://www.designers-guide.com/Analysis/sc-filters.pdf) as well?

So far, I have not found a way to realize an ideal sample-and-hold that works with the PAC, PXF, or PNoise analyses. The method using the idt() function that you describe under http://www.designers-guide.com/Forum/?board=rfsim;action=display;num=1033687038 does not seem to work for these analyses.

The method given by ronv which uses capacitors does work. However, the sample-and-hold operation is not ideal in this case due to the finite sample time and the finite decay during the hold period. In order to avoid numerical problems, it is always necessary to adjust these time constants to the time scale of the simulation. Also, the Verilog-A code is much more complex (and will probably take more time to simulate) than for the method using the idt() function.

Thanks a lot,

Frank

Title: Re: Device noise simulation of Sigma Delta modulat
Post by Ken Kundert on Jun 3^rd, 2003, 11:23am

Frank,
The model I used in the switched-capacitor paper (http://www.designers-guide.com/Analysis/sc-filters.pdf) was the one given in the hidden-state paper (http://www.designers-guide.com/Analysis/hidden-state.pdf). It is not ideal in that it has a finite aperature time. You can find it at http://www.designers-guide.com/Modeling/VerilogAMS/rf-models/sh/sh.va.

I currently know of no purely ideal sample-and-hold models that work with SpectreRF's small-signal analysis. However, if you are doing a noise analysis, using the strobed noise analysis (time-domain noise) works well.

-Ken