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Simulators >> Circuit Simulators >> changing the absolute value of a capacitance?
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Message started by vakilia on May 30^th, 2003, 1:31pm

Title: changing the absolute value of a capacitance?
Post by vakilia on May 30^th, 2003, 1:31pm

Hello;

I am simulating this switched capacitance charge amplifier that needs a changing capacitance to simulate the change of a mechanical capacitive sensor at its input. Of course I can do linear sweep on the capacitance value using parametric sweep of Spectre or use a varactor diode(hspiceS model in analogLib)which is not really like a mechanical changable capacitance. Is there any easier way to just simulate the absolute value of the capacitance with any time function like sine or so with no need to simulate the capacitance as a VCCS like the way that varactor hspiceS model in analogLib does?
I mean just using a way like parametric sweep but with arbitrary function of time rather than linearly sweeping?

Thanks
Babak

Title: Re: changing the absolute value of a capacitance?
Post by Andrew Beckett on Jun 2^nd, 2003, 12:24am

A voltage controlled capacitor (I think it will be called vccap) is planned
for spectre later this year. However, in the meantime you can quite easily
implement this kind of thing in Verilog-A. Here's an example of
a piece-wise linear capacitor which could be a starting point
for what you want to model:

Code:

`include "discipline.h"
`include "constants.h"

//pwlCap model, may be used for voltage controlled capacitor

//Model will emulate a capacitor that varies with voltage
//in a pwl form. This example is a capacitor that varies
//linearly for V=0 to V1, stays constant for V1 to V2, and
//again increases per a specified slope for V2 to V3. Performance is
//symmetric.

module pwlCap(vp, vn);
inout vp, vn;
electrical vp, vn;
parameter real c_base = 3u from (0:inf); //Base capacitance at V1=0
parameter real c_V2 = 5u from (0:inf); //Capacitance at V2
parameter c_slope = 3 from (0:inf);
parameter real V1 = 2 from (0:inf);
parameter real V2 = 3 from (0:inf);
parameter real V3 = 4 from (0:inf);

real c;

analog begin

if (( abs(V(vp,vn))>0 )&&( abs(V(vp,vn))<V1 ))
c=c_base+(V(vp, vn))*(c_V2-c_base)/V1;
else if (( abs(V(vp,vn))>=V1)&&( abs(V(vp,vn))<V2 ))
c=c_V2;
else if (( abs(V(vp,vn))>=V2)&&( abs(V(vp,vn))<V3 ))
c=c+c_slope*(V3-V2);
else
$strobe("Illegal Value");

I(vp, vn) <+ ddt(c*V(vp, vn));

end
endmodule

Regards,

Andrew.

Title: Re: changing the absolute value of a capacitance?
Post by Mighty Mouse on Jun 2^nd, 2003, 10:57am

Andrew's capacitor is nonlinear, whereas I believe a linear time-varying capacitor is what was requested. The following is a Verilog-A model for a linear time-varying capacitor. You did not indicate what kind of time variation you were looking for, so I just made the capacitance vary sinuoidally.

Code:

`include "discipline.h"
`include "constants.h"

// Linear capacitor whose capacitance varies with time.
// The variation is sinusoidal.

module tvCap(p, n);
inout p, n;
electrical p, n;
parameter real c = 1p from (0:inf); // average capacitance
parameter real cp = 0 from (0:c); // peak variation in capacitance
parameter real per = 1u from (0:inf); // period of variation

analog begin
I(p,n) <+ ddt((c+cp*sin(2*`M_PI*$abstime/per))*V(p,n));
bound_step(per/10);
end
endmodule

The bound_step is used to make sure the time step of the simulator is small enough so that the simulator does not ignore the variation (without it you will occasionally find the simulator stepping only on the nulls of the sinusoid).

Be aware that the nonlinear capacitor model that Andrew gave does not conserve charge. Remember, that when formulating nonlinear capacitor models, always formulate the model in terms of charge, and differentiate the charge to get current.

- MM -

Title: Re: changing the absolute value of a capacitance?
Post by vakilia on Jun 2^nd, 2003, 3:11pm

Thank you for all the helpful comments;

I tried to use Mighty Mouse's code (sorry! couldn't figure your real name) and the following error showed up;

Error found by spectre during SpectreHDL compile.
... , line 15:
"I(vp,vn) <+ ddt((c+cp*sin(2*`M_PI*$abstime/<<--? per))*V(vp,vn));"
... , line 15:
Error: syntax error

It seems the compiler can not accept $abstime keyword. So what I did, I used abs($realtime) instead of $abstime and it worked.

The time varying capacitance is working perfectly and I can change the value of the capacitance independant of the voltage across it!

Again thanks alot,
-Babak

Title: Re: changing the absolute value of a capacitance?
Post by Andrew Beckett on Jun 2^nd, 2003, 10:12pm

Thanks Mighty Mouse for the rather better example than
I gave...

Babak, the reason why $abstime didn't work for you
was probably that you're using an older version of
spectre which doesn't support the newer revisions
of Verilog-A where $abstime is preferred to $realtime.
Note, you don't need to do the abs($realtime), because

$realtime should be positive (actually, I can think of one case where it wouldn't, when using skipdc=sigrampup in transient)
even so, the model would be fine with negative
(but advancing in a positive direction) time values

Regards,

Andrew.

Title: Re: changing the absolute value of a capacitance?
Post by Voldemort on Feb 27^th, 2004, 10:01am

Hi Mighty Mouse,
I simulated your code for the time varying capacitor in spectre by biasing the p side of the cap with 5V and the n side with ground and running a transient anaylsis for 10m. I chose c = 1pf, cp=0.5p and per = 1m.

I plotted the current at the p node as a function of time and I noticed that it was centered around zero. I thought it should be centered around 5pA. (5V * 1pF) or some non-zero value. Am I making a mistake in my assumption ?. Furthermore changing c does not have any effect on the output current.
I assumed, since c is a constant and V(p,n) is time varying the first term inside the differential should be evaluated to a non-zero value...

Thanksl

--- I realized my mistake.

V(p,n) is a constant. So, the output should be centered around zero.

Thanks