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Design Languages >> VHDL-AMS >> Use of LEs by for statement
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Message started by Alair Dias Júnior on Sep 1^st, 2003, 7:12am

Title: Use of LEs by for statement
Post by Alair Dias Júnior on Sep 1^st, 2003, 7:12am

I'm using the altera Quartus II to implement some logic in a ACEX FPGA. Somewhere in my code, I use the for statement and I wanna know how it is configured by the compiler in the FPGA. Does it use the clock signal to "loop" the for or does it build a sequencial array of gates to do it?

Thanks

Title: Re: Use of LEs by for statement
Post by Akalya on Nov 7^th, 2003, 3:58pm

My guess would be that it uses sequential logic to implement a "For" loop. It does have limitations due to propagation delay.

Akalya.