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Simulators >> RF Simulators >> Trouble with Pnoise Switched Cap Simulation
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Message started by analogben on Nov 17^th, 2003, 8:02am

Title: Trouble with Pnoise Switched Cap Simulation
Post by analogben on Nov 17^th, 2003, 8:02am

I am running a simple switched cap simulation that consists of an ideal switch, a series resistor, and a capacitor. I am using the veriloga sample-and-hold block
provided on this website to sample the output, and I have allowed greater than
10 time constants to pass before performing any sampling or hold operation.

I would expect the noise density of this circuit to be consistent with having kT/C integrated over a bandwidth of 1/2 the sampling rate. I would also expect
the circuit noise be independent of the series switch resistance.

The results of the simulation, however, show an output noise density lower than what would be expected from kt/C. (The density, is, however, larger than 4kTR... and I have verified that the verilog SH block samples the capacitor during the hold phase). The simulated noise density is also a strong function of the series switch resistance.

I have also noticed that when I run a sim using a MOS switch, that there is a large 1/f component to the simulated noise contribution. This is also somthing I would not expect to see.

Any suggestions?

Ben
???

Title: Re: Trouble with Pnoise Switched Cap Simulation
Post by Ken Kundert on Nov 17^th, 2003, 9:21am

Have you read the paper on "Simulating switched-capacitor filters with SpectreRF" at www.designers-guide.com/Analysis/? It talks about setting maxsidebands to get the desired accuracy (setting it too low would result in the noise being under estimated), and what the effect of the trailing track-and-hold will have.

Concerning the flicker noise, I don't know what to suggest other than verifying that the flicker noise parameters on your model are correct and then carefully examining your circuit to determine how the flicker noise is propagating through your circuit (the noise contribution summary would be helpful here).

-Ken

Title: Re: Trouble with Pnoise Switched Cap Simulation
Post by analogben on Nov 19^th, 2003, 11:26am

Thanks for your help, Ken.

I was able to get the noise density at higher frequencies to come close to
theory by setting maxsidebands properly as suggested in your article.

I am still seeing a considerable amount of MOSFET 1/f noise in the simulation
results, however. According to the "pss-td" results, the NMOS switch
is conducting 33fA at the sampling instance. An ac noise simulation of the same NMOS device biased at 33fA shows no 1/f noise. Since the cap is virtually settled at a point at which there is virtually no 1/f noise generated, I would expect there to be no physical mechanism by which 1/f noise propagates to the output.

Another interesting thing I noticed is that the flicker noise contribution is appearing at non-zero sidebands. (I simulated this by selecting various
single noise sidebands in the pnoise analysis).

Regards,

Ben

Title: Re: Trouble with Pnoise Switched Cap Simulation
Post by Ken Kundert on Nov 20^th, 2003, 10:17am

I agree with your comments about flicker noise in the switches, but it is puzzling that the noise is coming from the non-zero sidebands. Perhaps you can describe the circuit in more detail. Is there frequency conversion purposely occuring in this circuit?

-Ken