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Measurements >> Phase Noise and Jitter Measurements >> plot phase noise for PLL
https://designers-guide.org/forum/YaBB.pl?num=1070650257

Message started by CDR on Dec 5^th, 2003, 10:50am

Title: plot phase noise for PLL
Post by CDR on Dec 5^th, 2003, 10:50am

In Ken's paper is "modeling jitter in PLL_based frequency synthesizers".I plot the power spectral density of VCO phase,the frequency range is from 300Hz to 100KHz,if I want to see further frequency to 100M,how could I set the matlab script to get the waveform?

And Kundert indicates the displayed frequency domain is fout/2 to fout/nfft,could we make a little further to see the phase noise in wider range?

Title: Re: plot phase noise for PLL
Post by Ken Kundert on Dec 5^th, 2003, 11:41am

The maximum frequency for the PSD is constrained to be f_out/2. There is no way around that. However, you can increase f_out. To do so you will need to pull at least part of the divider out of the VCO model. Currently, the VCO model models both the VCO and the divider. It does so to reduce the output frequency, which makes the model more efficient. In the example, the divide ratio is 10,000. If you pulled all of that out, the maximum frequency in the PSD would be 10,000 times higher, but the simulations would be 10,000 times more expensive. This might be viable if you switched to event-based modeling in Verilog-AMS or C. However, you can just pull out a fraction of 10,000, say a factor of 10. That would give you a higher upper bound on your PSD frequency, but would not make the simulation overly expensive (such that it requires a rewrite).

One generally does not need to make the maximum frequency for the PSD very high because once you get beyond the dynamics of the loop, the output noise response simply drops in proportion to 1/f². This allows you to easily predict the high frequency phase noise performance from what you have. For example, in the paper S_phi(100kHz) = -45dBc. It will drop at a 20dB/dec rate, making it -105dBc at 100MHz.

-Ken