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Design >> Analog Design >> Noise Analysis
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Message started by akenovic on Jan 5^th, 2004, 6:20pm

Title: Noise Analysis
Post by akenovic on Jan 5^th, 2004, 6:20pm

Hi All,

I have designed circuits for on-chip low swing signaling (0 - 800mV swing). I plan to implement this circuit as a standard cell and I would like to do a noise analysis for my circuit. I would llike to investigate supply noise, wire coupling noise and transistor noise sources. This cell will be used in a larger digital system running at 50Mhz to 200MHz. Being a rookie, I am not sure if I should be worried about coupling noise at such speeds? Any help will be immensly appreciated.

Thanks.

Victor

Title: Re: Noise Analysis
Post by okguy on Feb 9^th, 2004, 5:35am

Any digital will make noise when toggling, what ever its clock frequency ! :o
And if it 2 small inverters, the noise will be much less than a see of gates ! :P

Title: Re: Noise Analysis
Post by akenovic on Feb 9^th, 2004, 6:17pm

So Okguy, what is the point of your reply? How does it help me? My question was not meant as some joke so get serious. I am not amused.

Title: Re: Noise Analysis
Post by Aigneryu on Feb 9^th, 2004, 9:07pm

Hi, akenovic

The noise coupling from digital portion to analog one
is difficult to estimate from the preliminary degin phase in mixed-signal circuit (your low triggered circuit may be treated so ). Most coupling is coming from poor layout or board design.

The noise analysis after layout is important for a unexperienced
mixed-signal designer. Maybe you can use some softwares that can help you to justify your circuit after layout. For example, substratestorm.

You can also read Ken's paper on the subject of supply noise. which can be downloaded on this site, and the cadence whitepaper "Substrate Noise Analysis of Mixed-Signal Ics"

Hope they can give you an example or a startup.