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Simulators >> RF Simulators >> SpectreRF PLL design
https://designers-guide.org/forum/YaBB.pl?num=1074208138

Message started by Dan on Jan 15^th, 2004, 3:08pm

Title: SpectreRF PLL design
Post by Dan on Jan 15^th, 2004, 3:08pm

I have a few general questions concerning the selection of analog simulation analyses for PLL design. I have simulated my VCO, PFD, and Frequency divider blocks individually with transient and PSS analyses. However, I run into problems when attempting to run a system level PSS analysis. I assume this is due to the presence of the VCO which will produce frequencies that are non-integer multiples of the fundamental frequency. Can PSS analysis be used to find the steady state input voltage to the VCO in a full PLL model? Or is this value only determined through lengthy transient analyses? I'm assuming that the phase and jitter noise of the system will be determined by performing PSS followed by Pnoise, etc. for the individual blocks and building a phase domain model based on the results (per Ken's paper). Thanks,

Dan

Title: Re: SpectreRF PLL design
Post by Jitter Man on Jan 15^th, 2004, 10:38pm

Ken addresses this topic in his paper. See section 1.2 - Direct Simulation. Basically, you can simulate the whole PLL with PSS if the PFD/CP does not have a deadzone and if the divide ratio is not too great. You just have to set tstab large enough so that it takes you to lock.

[glb]Jitter Man[/glb]