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Design >> Analog Design >> CMOS Switch on-resistance
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Message started by boa on Feb 9^th, 2004, 1:54pm

Title: CMOS Switch on-resistance
Post by boa on Feb 9^th, 2004, 1:54pm

I am sorry for asking very basic things but anyway..
How can I measure CMOS switch on-resistance in a simulator?

I am a bit confused since I've seen 2 variants:

1. The sources of NMOS and PMOS are connected to sweeping DC voltage, the gates are connected to Vdd and Vss consequently and the drains are connected to a capacitor whose other plate is connected to the ground. There is a small fixed Vds voltage for transistors (DC source between source and drain).

2. The drains are connected directly to the ground (and there is no fixed Vds voltage across the switch).

Which variant is better for estimating the settling time of SC circuits??

Title: Re: CMOS Switch on-resistance
Post by Paul on Feb 10^th, 2004, 12:17am

Hi boa,

personnally I would use the first method, obtaining the switches on-resistance as the ratio between the small Vds voltage (e.g 100mV) and the current flowing through this Vds voltage source. You don't need the capacitor as you are doing a DC sweep.

Notice that the on-resistance depends a lot on the voltage applied with respect to ground (the swept DC voltage). To be sure your design will work, you should take the worst-case resistance inside your useful signal swing. The signal swing may depend on the place of the switch in the schematic.

Paul

Title: Re: CMOS Switch on-resistance
Post by erikwanta on Feb 11^th, 2004, 6:16pm

Can you not use the ron value calculated by spectre in the OP results?