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Design Languages >> Verilog-AMS >> Missing hdl.var!!Why?
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Message started by Aigneryu on Feb 18^th, 2004, 9:03pm

Title: Missing hdl.var!!Why?
Post by Aigneryu on Feb 18^th, 2004, 9:03pm

I tried to open a new verilogams view in the lib manager of cadence design environment.

but when I saved the edited netlist file, an error message showed up and told me that "parsing of verilog-ams files produced warnings..."

and then I was told that "ncvlog : *W, DLNOHV : Unable to find a 'hdl.var' file to load in ".

what does it means?
I checked the folder of the cell, there was no hdl.var.

Title: Re: Missing hdl.var!!Why?
Post by Andrew Beckett on Mar 4^th, 2004, 10:17am

Generally with AMS Designer (along with the digital simulation tools, such as ncvlog, ncsim etc) it requires you to have
an hdl.var file in one of a number of search locations
(typically your working directory).

You don't need that much in it. Usually something like
this will suffice:

Code:

SOFTINCLUDE $AMSHOME/inca/files/hdl.var
# setup use5x by default
define ncuse5x
define cdslib ./cds.lib

You might set up the path to transistor models if you're
simulating at transistor level, although this can be
done through the UI now with AMS Designer.

Andrew.