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Design >> Analog Design >> What is basic assuption?
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Message started by newmedia on Mar 8^th, 2004, 7:14pm

Title: What is basic assuption?
Post by newmedia on Mar 8^th, 2004, 7:14pm

Hello, everybody.

I’m beginner of jitter and phase noise related issue. What I want to do is design a PLL and do jitter and phase noise modeling. My target process is TSMC 0.18um. During web surfing, I found the Ken’s website.

I took a look the ken’s paper “Predicting the phase noise and jitter of PLL-based frequency synthesizers”. That paper was awesome! However I think I don’t understand basic assumption. Somebody can tell me whether I’m correct or not

The Ken’s paper starts with the direct simulation and then Monte Carlo-based methods. My confusion starts here. [glb]“Did Ken assume that PLL layout is done?”[/glb] We can extract parasitic R & C after actual layout. It means if there are problems, we have to change layout again and again. If the Ken’s paper assumed top-down design, it makes sense. But there is another problem. How he can model parasitic components of PLL?

If some have good explanation, please, let me know.

J.J.

Title: Re: What is basic assuption?
Post by newmedia on Mar 9^th, 2004, 6:04am

Hello, everyone.

I checked this forum this morning, and I saw someone, I forgot his username, wrote a reply and then I realized he removed it. He asked me that do I have experience at SpectreRF, and recommend read “Simulating switched-capacitor filters with SpectreRF” paper.

I’m digital circuit guy, so I usually used Spectre not SpectreRF, but I read the paper, “SpectreRF tutorial” from cadence about one month ago.

I also checked “Simulating switched-capacitor filters with SpectreRF”. In that paper, Ken mentioned about back annotation functionality, it can be good solution. During iterative design process, back annotation can be good solution.

Let me summarize my conclusion.
1. Design PLL. At this time, use assumption about parasitic effect.
2. Do pre-layout simulation
3. Layout PLL
4. Back annotation
5. Do post-layout simulation
6. Modify layout
7. Iterate 4,5,6 until you are satisfied with the result.

Am I right?

j.j.

Title: Re: What is basic assuption?
Post by Paul on Mar 9^th, 2004, 11:43am

Hello JJ,

you are more or less correct, except that you should try to have sufficent assumptions to avoid cycling several times between layout and design phases.

Paul

Title: Re: What is basic assuption?
Post by fehler on Sep 22^nd, 2004, 7:47am

First of all, I have to confess I have not read through
Ken's paper. I only have a glance on it. But, as I know,
Monte Carlo method in jitter/phase noise simulating
if of no business to layout. In this way, we give a random variable to stand for the noise, not the mismatch. For example, we want to represent a mosfet
noise in simulation, we use a step series, whose amplitude is varied with time. This amplitude will be
determined by Monte Carlo. Is it the case?

Just an idea as reference. Wish it can help.