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Simulators >> Circuit Simulators >> pll ckt simulation hellp!
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Message started by jeffyan on Mar 11^th, 2004, 7:05am

Title: pll ckt simulation hellp!
Post by jeffyan on Mar 11^th, 2004, 7:05am

i am woking on pll ckt design,and i do the .tran simulation by hspice,however the display of awaves is very strange: there is no delay between signals,(every positive and negtive edge is very steep), and the pulse (up)&(down) which are swith control both become a steep thread! however the phase between the refrence clock and output of VCO is locked!
i don't know whether it is the problem of hspice.
i'd like to know where's problem?
how can i get the right result?
hoe to set .option card?

thanks

Title: Re: pll ckt simulation hellp!
Post by skt on Apr 2^nd, 2004, 4:35pm

>>there is no delay between signals,(every positive and negtive edge is very steep),

i assume you are talking about the output of the VCO. yes, if your VCO operates at very high output frequencies, you have outputs with steep positive and negative edges... this is due to the time delay around the loop being very small

>>and the pulse (up)&(down) which are swith control both become a steep thread! however the phase between the refrence clock and output of VCO is locked!

i think this is because you are feeding the output of the VCO (which had steep edges) to the PFD and comparing it with an ideal input clock. Put a buffer after the VCO so that you get a pulse waveform and then compare it with the input clock

Surya