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Simulators >> Circuit Simulators >> who can explain the hspice result?
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Message started by ppdd on Mar 17^th, 2004, 4:16am

Title: who can explain the hspice result?
Post by ppdd on Mar 17^th, 2004, 4:16am

Hi

I want to simulate a pulse thru capacitor to see the voltage drop.below is my netlist:

vin in 0 pulse 1.25 2.75 1ns 1ns 1ns 5ns 10ns
c1 in xtl 2n
mesd xtl vdd vdd vdd pmos w=300u l=0.35u
mn1 out xtl 0 0 nmos w=5u l=0.35u
mp1 out xtl vdd vdd pmos w=12u l=0.35u
vdd vdd 0 dc=3.3v
**

when i add an esd protection pmos in the node of xtl, i found the voltage at xtl is lifted,the low voltage is 2.7v, the high voltage is about 3.3v. but if i replace this pmos esd using nmos device(also a esd protection purpose), the voltage at xtl is dropped, the low voltage is 0, and the high voltage is 1.5v.

so i cannot explain that result, who can tell me the reason? thanks

Title: Re: who can explain the hspice result?
Post by sutapanaki on Mar 17^th, 2004, 11:49am

Well, your xtl node is supposed to be a floating node. However, if you connect the esd pmos transistor, there is a reverse biased diode from bulk to drain, which will charge the node to some voltage. If you don't specify initial conditions for the voltage on xtl, the simulator assigns there some voltage. The higher this voltage the worse, because suppose the xtl voltage is @ 3.3 initially and the cap is charged to 3.3-1.25=2.05. When your input source goes to 2.75 the xtl voltage should go to 4.8v which will turn on the bulk-drain diode of the esd pmos transistor and you'll have big bulk current. Because your cap is big and your pulse time is small, you basically don't have enough time to discharge the cap and you see the voltage shifted up.
Run your simulation and check for bulk current. Also, put initial conditions for the xtl voltage, play with different values for it and see how this affects the behavior.
If this is to be a real circuit, you'll need something to fix the foltage of xtl.

Title: Re: who can explain the hspice result?
Post by ppdd on Mar 17^th, 2004, 9:29pm

:D Hi sutapanaki, thank you.

You are right. The voltage at xtl node is affected by the initial voltage. I altered the initial voltage of xtl node and got the different curvers. But I don't know why the init voltage at xtl node is 3.3V using PMOS ESD while init voltage is zero when using NMOS ESD?

this is a real circuit. The pmos and nmos esd transistors are all in an IO pad. And we observed the voltage at xtl node is 0-1.5V(the pulse voltage is 1.25-2.75V).But the simulation result is totally different. So I am confused.

Thank you again.

Title: Re: who can explain the hspice result?
Post by sutapanaki on Mar 17^th, 2004, 11:03pm

If you use only a pmos esd transistor the xtl node gets charged to 3.3 through the drain-bulk diode (by the reverse current of it) - at least the simulator assumes so, since this diode is the only relatively conducting part connected to this node. Similar for the nmos esd only case, but there things happen towards ground. After all the simulation should start from some operating point.
Now, if this is a real circuit I just speculate that this is a crystal oscillator together with the inverter as an active element. If this is so, then there should be a resistor connected between the input and the output of the inverter for the purpose of setting the operating point and putting the inverter in its active region. In this case this resistor fixes the voltage of xtl and this node is not floating anymore. But this is only if my assumption about the real circuit is correct. If it is not, then I don't know.

Title: Re: who can explain the hspice result?
Post by Humungus on Mar 18^th, 2004, 11:40am

ppdd,

if both, n and p, esd transistors are in your circuit, then you should simulate with both of them connected. If that's the case, maybe the nmos esd could be more leaky and then the initial voltage is determined by it. That is Vin=0.

Also, if you got a swing from 0-1.5v in xtl when you apply your pulse from 1.25-2.75v (swing=1.5V) then everything could be logical if the starting point is 0v.

Also, if your simulation is long enough, you should see that your n esd should operate, because the quiscent voltage at xtl should be 0 with a peak swing of 0.75V around 0v.