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Design >> Mixed-Signal Design >> Is timing important for pipelined ADC?
https://designers-guide.org/forum/YaBB.pl?num=1079633368

Message started by potter on Mar 18^th, 2004, 10:09am

Title: Is timing important for pipelined ADC?
Post by potter on Mar 18^th, 2004, 10:09am

??? 1. Why non-overlap clk ? first i designed full system of pipelined by ideal opamp, and switches but real comparators. I use 2 V supply so i set switch threshold 1V. It OK with ideal comparator and one stage simulation, but when i use my real comparator and connect the secound stage there is something wrong with the output of the first stage. The first time i guess that may be cause Cparacitic of the comparator of the next stage so i test by simulate with C load and switch but it not the problem. Who know my problem please introduce me something. :-[
i use simple 2.5bit switched capaciter circuit .