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Design Languages >> Verilog-AMS >> cadence/verilog ams environment
https://designers-guide.org/forum/YaBB.pl?num=1081012596

Message started by Elf_ThatsMe on Apr 3^rd, 2004, 9:16am

Title: cadence/verilog ams environment
Post by Elf_ThatsMe on Apr 3^rd, 2004, 9:16am

I have a couple of different designs modules in a single cadence library. Once I was ready with all the modules required, I created a config view using HED. Now I am not sure what I did wrong, but I have ended up with alllll my verilogams views having the same "my_design_top" level view's code !!!!( the one I created the config view with).
Can someone pls clarify as to what went wrong and why !! :-/

thanks,
Elf.