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Design >> Mixed-Signal Design >> digital library for mixed-signal
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Message started by ravi on Apr 16^th, 2004, 1:51am

Title: digital library for mixed-signal
Post by ravi on Apr 16^th, 2004, 1:51am

Hello,
What are the special considerations to be taken when designing library of digital gates for a mixed-signal design when compared to a standard digital-cell library for a digital ic.

thanks
ravi

Title: Re: digital library for mixed-signal
Post by Andrew Beckett on Apr 17^th, 2004, 11:43pm

There aren't really any. Most mixed-signal designs are done using standard digital cell libraries. Certainly all the mixed signal designs I've done have used normal digital cell libraries. Occasionally you need a digital cell (in the analog parts of the design) which isn't quite right in the digital library (wrong drive strength, thresholds etc) which you might need for a specific purpose, but in general I can't think of any special requirements.

Of course, it's useful to have those digital cell libraries using inherited connections, so if you need to use the digital cells on an analog supply, it's easy to do so, but apart from that I'd say there are no special requirements.

Regards,

Andrew.

Title: Re: digital library for mixed-signal
Post by ravi on Apr 18^th, 2004, 11:30pm

Thanks a lot for your reply Beckett. But what do your mean by 'inherited connections'?

thanks
Ravi

Title: Re: digital library for mixed-signal
Post by Andrew Beckett on Apr 19^th, 2004, 1:19pm

Often digital cell libraries, if they have schematics, have the power supplies as global connections rather than pins. This is because digital designers don't normally want to have to connect up the power supplies in their verilog code - which may have come out of synthesis anyway.

The trouble with global supplies is that often you don't want digital components which are in an analog portion of the design to be on the same supply as the rest of the digital - you may want them to be on an analog supply. But global means global, and so global supplies prevent you from being able to use multiple supplies.

Cadence DFII has this mechanism called "inherited connections" which allows a connection inside a cellView to inherit it's connection via a property set one or more levels above in the hierarchy.

For example, I can define a net in a schematic, with a net expression on it saying that the net is governed by a property called "pvdd", with a default value vdd!
This means that if I don't do anything, and use it as normal, it will end up connected to the global net vdd!.
However, I could set a property value for pvdd on an instance, several levels up the hierarchy, indicating that pvdd to should bind to a net (at that level) called "avdd".

What happens for many netlisters is that the netlister will then insert extra connections through the hierarchy to wire this up, although the schematic doesn't need to be physically wired up. Other simulators (like AMS Designer) can resolve these inherited connections at elaboration time (effectively when the hierarchy is flattened).

I could then have one block using the cell which has pvdd set to avdd, another set to bvdd, and another where it is not set and defaults to vdd!. Consequently I have three blocks, using the same cell, which doesn't have pins for the power supply, yet they are connected to different things.

That's the idea - it's very useful indeed. You can think of it as a means of making connections via properties, rather than via physical wires in the schematic.

Regards,

Andrew.

Title: Re: digital library for mixed-signal
Post by ywguo on May 13^th, 2004, 7:51am

Hello,

I have never used the inherited connections. But I always modify the symbol of the standard cell, puting pin vdd and vss on it. Then I can connect them arbitrarily to vdd, vss, avdd, avss, etc. It is more visual in the schematic. :)

As to some possible special requirement, what I can thought is that the P/N ratio is too small sometimes. Then the rising edge and falling edge is not symetrical, rising edge slower, and falling edge faster.

For high speed mixed signal circuit, that is a problem. For e.g., serdes, PCI-express, SONET, those circuits operates above GHz. The designer must be very careful to keep the rising edge and falling edge balance. Otherwise the clock signal above GHz will become distorted, even disapear.

For that design, it is a bad news that the standard cell often have a low P/N ratio in order to get high density. Most standard cells have P/N ratio of about 1.5 to 2, while the Beta of PMOS is more than 3 times of the Beta of NMOS in very deep submicron process, even 4 ~ 5 times.

So sometimes the designers have to design the cells by themselve.

And now I am designing pipelined ADC. In this design I use some standard cell. I found the nonoverlapping clock has slower rising edge, about two times of falling edge. I suspect that affect the open and close of the complement MOS switch. So I am checking it and maybe rebuild all the digital cells.

Best regards,

Yawei Guo

Title: Re: digital library for mixed-signal
Post by Andrew Beckett on May 13^th, 2004, 10:52am

Quote:

I have never used the inherited connections. But I always modify the symbol of the standard cell, puting pin vdd and vss on it. Then I can connect them arbitrarily to vdd, vss, avdd, avss, etc. It is more visual in the schematic.

That's one of the main goals of inherited connections - you can have a set of digital standard cells that you don't need to copy and modify to use in the analog domain (unless of course you need to change the design). You can still follow the connections using inherited connections.

Andrew.